Before the advances of FinFET technologies, semiconductor devices were arranged whereby their active areas were laid out on a horizontal plane, side by side each other. As technology continues to advance and the necessity to pack more semiconductor devices on a single chip become more pressing, the need to devise a new arrangement is of paramount importance.
FinFET technologies provide a viable alternative to pack hundreds of millions of semiconductor devices within a single chip while still reducing the area of the chip. In FinFET technologies, because the active areas of these semiconductor devices are placed vertically, the total required planar area is reduced.
FinFET also offers various design characteristics that can reduce leakage. As one example, active areas are built on an insulator, which minimizes leakage, instead of a semiconductor substrate typical in older technologies. As another example, because FinFET technologies allow the channel to wrap around the body between the source and the drain, a double gate having gates on each vertical side of the depletion region is possible whereby the double gated device provides a lower channel leakage current than a single gated device. As a further example, leakage in a fin of the FinFET is reduced simply because of the reduction of the volume of the body.
However, current FinFET technologies do not provide an easy mechanism to characterize devices in designs and in production, because there is no easy way to make contact to all four terminals (the source, the drain, the gate, and the body) of a semiconductor device. When the source, the drain, and the gate are available, the body is unavailable because there is no way of reaching the body when the device is on top of an insulator. Without electrical information from all four terminals, adequate information regarding the device cannot be fully retrieved, thus limiting the viability and effectiveness when deploying FinFET technologies.
Desirable in the art of semiconductor designs are additional designs for better enabling device characterization in a FinFET device environment.